Depending on the applications and performance aimed at, different types of memories are used.
Thus, SRAM type memories, or static random access memories, offer ultra-fast write times, required for example during the computations by a microprocessor. The major drawback of these memories is that they are volatile and that the relatively large size of the memory element does not enable a high storage capacity to be obtained in a moderate volume.
The DRAM type memories, or dynamic random access memories, which perform the storage of electric charges in capacitors, offer a large storage capacity. These memories, however, have higher write times (a few tens of nanoseconds) than those of SRAM type memories and are also volatile, the information retention time being in the order of a few tens of milliseconds.
Conversely, for applications which require an information storage even when the voltage is shut off, solid state memory devices are also known which preserve information in the absence of power supply: these devices are called non-volatile memories. Thus, for numerous years, different technological solutions have been developed, and have led to the availability of non-volatile memories that can be electrically written and erased. For example, mention might be made of the following:                EPROMs (“Erasable Programmable Read Only Memories”), the content of which can be electrically written, but which have to be subjected to a UV radiation to erase stored information;        EEPROMs (“Electrically Erasable Programmable ROMs”), the content of which can be electrically written and erased, but which require, for being manufactured, semiconductor areas larger than EPROM type memories, and which are therefore more expensive to make.        
Given that the two above mentioned solutions have a limited application, the manufacturers have been searching for an ideal non-volatile memory, which would combine the following characteristics: electrical writing and erasing, high density and low cost per bit, random access, short write and read times, good endurance, but also low power consumption and low supply voltage.
There are also non-volatile memories, called Flash memories, which do not have the aforementioned drawbacks of EPROM or EEPROM memories. Indeed, a Flash memory is formed by a plurality of memory cells that can be individually electrically programmed, wherein a great number of cells, called a block, a sector, or a page, can be simultaneously electrically erased. Flash memories combine both the advantage of EPROM memories in terms of integration density and the advantage of EEPROM memories in terms of electrical erasing.
Moreover, the durability and low electric power consumption of Flash memories make them interesting for numerous applications: digital cameras, cell phones, printers, personal assistants, laptop computers, or even portable sound reading and recording devices, USB keys, etc. Moreover, Flash memories do not have mechanical elements, which provides them with a quite high impact resistance. In the “all-digital” age, these products have been largely developed, allowing a boom in the market of Flash memories.
Most commercial non-volatile Flash memories use charge storage as a principle for information coding. In practice, a charge trapping layer (generally of polysilicon, or a dielectric such as SiN) is packaged between two dielectrics in the gate stack of a MOS transistor. The presence or absence of charge in this medium modifies the conduction of the MOS transistor and enables the memory state to be coded.
More recently, other types of rewritable non-volatile memories have emerged to reduce voltages and programming times of Flash memories; mention might be made in particular of ferroelectric memories (FeRAM, “Ferroelectric RAM” memories), based on bias switchover, or magnetic memories (MRAM memories or “Magnetic RAM”) which use the direction of the residual magnetic field in the active material. However, FeRAM and MRAM memories have difficulties which restrict their downsizing.
In order to overcome these difficulties, variable resistance memories (called RRAM, “Resistive RAM” memories) are known; the latter attract much attention nowadays. The resistive type memories can have at least two states, “off” or “on”, corresponding to switching from a resistive state (“HRS” state) to a less resistive state (“LRS” state).
Variable resistance random access memories are attracting much attention nowadays, in particular due to their low electric power consumption and high operating rate.
The binary data 0 or 1 are stored in a metal/insulator/metal (MIM) structure having two distinct resistance states. FIG. 1 represents the structure of a MIM type RRAM memory cell 1. This device 1 is formed by a stack including an active storage area 2 provided between a lower conducting electrode 3 and an upper conducting electrode 4.
Thus, the resistive type memory cell can reversibly switch over from a high resistance state “HRS”, also called “OFF” state, to a low resistance state (“LRS”) or “ON” state. Therefore, it can be used to store binary information.
The write mechanism is called SET within the scope of RRAMs and consists in switching from the HRS state to the LRS state. To erase information, the active material is switched from the LRS state to the HRS state, the erase mechanism being called RESET. The LRS and HRS states are both conducting (of course with a better conduction of the LRS state in comparison to the HRS state); but in the initial state, the active material of the active storage area 2 is insulating (PRS (“Pristine Resistance State”) state). A first electrical stress thus has to be applied to the virgin memory cell in order to generate the LRS state for the first time. The associated process, called FORMING, consists of a partially reversible breakdown of the active material, that is after switching from the PRS insulating OFF state to the LRS conducting ON state, the resistance of the conducting ON state can be switched over to the HRS state with a lower electrical stress (RESET operation).
The resistance changing phenomenon is observed in different types of materials, which suggests different operating mechanisms. Thus, several types of resistive memories can be distinguished.
The field of the present invention more particularly relates to two categories of resistive memories:                the memories including an active area based on an oxide-based active material (OxRRAM memory or “Oxide RRAM”) such as a binary oxide of a transition metal;        the memories including an active area based on an ion conducting material (CBRAM memories or “Conductive Bridging RAM”) forming a ion conducting solid electrolyte provided between an electrode forming an inert cathode and an electrode including a ionisable metal portion, that is a metal portion that can readily form metal ions, and forming an anode.        
The operation of CBRAM memories is based on the formation, within the solid electrolyte, of one or more metal filaments (also called “dendrites”), between its two electrodes when these electrodes are brought to appropriate potentials. The filament formation allows a given electrical conduction to be achieved between both electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the filament distribution, and thus to modify the electrical conduction between both electrodes. For example, by inversing the potential between the electrodes, it is possible to do away with or reduce the metal filament, so as to remove or dramatically reduce the electrical conduction due to the presence of the filament. In the “HRS” state, metal ions from the ionisable metal portion of the soluble electrode are dispersed in the entire solid electrolyte. Thus, no electrical contact is set between the cathode and the anode, that is between the upper electrode and the lower electrode. The solid electrolyte includes a high resistivity electrically insulating area between the anode and the cathode. When a positive VSET potential is applied to the anode, a redox reaction occurs at this electrode, creating mobile ions. The ions then move in the electrolyte under the effect of the electric field applied to the electrodes. When arrived at the inert electrode (the cathode), the ions are reduced, causing the growth of a metal filament. The filament preferentially grows in the direction of the soluble electrode. The memory then switches to the “LRS” state when the filament allows contact between the electrodes, making the stack conducting. This phase makes up the “SET” of the memory.
To switch to the “HRS” state (“RESET” phase of the memory), a negative VRESET voltage is applied to the anode, causing the dissolution of the conducting filament.
As regards OxRRAM memories, as for the CBRAM memories, the filament model is widely consensual. Therefore, it also relies on the formation and breaking of one or more conduction paths (conducting filaments) in the oxide matrix, connecting both electrodes. The formation and breaking of conducting filaments are ascribed to the presence of oxygen vacancies.
It is important to note that, in the case of OxRRAMs as in the case of CBRAMs, the SET operation enables the memory cell to be switched from a HRS high resistance state to a LRS low resistance state. As discussed above, the SET is made by applying a sufficient voltage VSET at the terminals of the memory element. The transition between the high and low resistance states (close to an oxide breakdown in the case of an OxRRAM memory) is very fast and results in a sharp current increase when the VSET voltage is reached. This increase is illustrated in FIG. 2. This sharp current increase is not auto-restricted. If nothing is made to control this increase, the current will increase up to very high values likely to cause a very high temperature increase and a destruction of the memory device. Therefore, it is desirable to restrict by compliance the current increase up to some value in order to achieve a low resistance state while keeping a memory device safe. This restricted current is indifferently called current limitation or current compliance.
The current limitation during the write operation can be made by different means such as a resistance or a transistor in series with the memory: adding a resistance or a transistor in series enables the current passing through the memory element and series resistance/transistor assembly to be limited.
The use of a resistance R (illustrated in FIG. 3) put in series with the memory element (herein an OxRRAM memory) enables the current to be limited. The presence of the series resistance enables the current which passes through the assembly to be limited once the OxRRAM cell is switched to the low resistance state. At the beginning of the write operation (SET), the OxRRAM memory is in a high resistance state (HRS). Thus, most of the applied voltage VApp between the resistance and the memory in series ends up at the terminals of the memory element (i.e. the voltage VR at the terminals of the resistance is negligible in comparison with the voltage VOx at the terminals of the memory). When the voltage at the terminals of the OxRRAM memory becomes sufficient (i.e. higher than the threshold voltage VSET), the switching occurs (switchover from the HRS mode to the LRS mode) and the current quickly increases. The voltage at the terminals of the series resistance R increases to “support” the extra voltage. This decrease in the voltage at the terminals of the memory cell thus limits the current increase in the memory.
The use of a series transistor (illustrated in FIG. 4) is very close to the use of the series resistance R. In the same way, upon writing, the current increase causes an increase in the voltage at the terminals of the series transistor. The benefit of using a transistor with respect to a series resistance is that it enables to control the limitation level using the gate voltage. The higher the gate voltage, the higher the saturation current. The transistor thus acts as a means for adjusting the current limitation in the OxRRAM memory.
One way for developing OxRRAM and CBRAM memories is information retention, that is the retention of the “HRS” state and the “LRS” state. It is attempted to improve the stability over time of the insulating and conducting ON states.
It has been demonstrated that the current limitation used during the SET write operation has a strong influence on the information retention performance.
Thus, in the paper “Improvement of data retention in HfO2/Hf 1T1R RRAM cell under low operating current” (Chen Y. Y. et al.—IEEE 2013), it is shown that the current limitation during the SET write operation has a high influence on the retention performance: the current limitation degrades the retention performance. In other words, a memory cell written with a current limitation IC1 has a better retention stability than when it is written with a current limitation IC2 lower than IC1. A decrease in the current limitation during the write operation produces LRS states with a higher resistance and a lower stability (i.e. a quicker increase in the resistance and thus a loss of information). This phenomenon is illustrated in FIG. 5 which represents the evolution of the current at a given voltage of 0.1V passing through a memory cell once written in a LRS state as a function of time, this evolution being obtained with two different current limitations: 40 μA and 10 μA. This evolution thus represents the evolution of the resistance of the LRS state as a function of time. The cell written with a limitation of 40 μA has a better stability than that written with a limitation of 10 μA (all the other experimental conditions being otherwise equal) and the SET initial resistance with a limitation of 40 μA is higher than the SET initial resistance with a limitation of 10 μA. The retention performance of the LRS state thus depend on the current limitation and thus on the level of the LRS resistance when writing.
Besides, it has been shown (cf. paper “Temperature impact (up to 200° C.) on performance and reliability of HfO2-based RRAMs” (Cabout T. et al.—IEEE 2013)) that the programming temperature of the memory (i.e. the temperature of the memory when the SET or RESET operation is made) has a very little effect on the resistance levels of the LRS and HRS states of these memories. The curves of FIG. 6 represent the evolution of the initial resistances at the LRS (bottom curve) and HRS (top curve) states as a function of the programming temperature applied (respectively during the SET and RESET operations). It is observed on these curves that the temperature has nearly no influence on the resistance levels. The resistance of the LRS state is thus the same regardless of the write temperature. It will be noted that the same is true for the resistance of the HRS state.